Provenance Record

Clear, well-structured News piece (713 words, within the 400-1200 range). Strong sourcing discipline: every claim is attributed inline, the article explicitly separates 'What We Know' from 'What We Don't Know,' and self-reported performance claims are flagged as such.

Personally read all 5 gzipped snapshots; all sha256 hashes match manifest (status 200, no archive fallback). source-0 (TechCrunch): confirms June 24 unveiling, Jalapeño name, Broadcom co-design/manufacture, OpenAI's own models assisting, Oct 2025 partnership announcement, inference focus, performance-per-watt claim. source-1 (Constellation): confirms 'nine months' co-development, 'used its own models to accelerate the design and optimization process,' Broadcom+Celestica integration, Tomahawk chips, 'reduces data movement and balances compute, memory and networking,' GPT-5.3-Codex-Spark in lab workloads, deploy by end of year, works with all LLMs, technical report promised. source-2 (Pulse 2.0): confirms first 'Intelligence Processor,' designed from scratch, 'performance per watt substantially better than current state-of-the-art systems,' works with current/future LLMs, and the Brockman, Hock Tan, and Richard Ho quotes verbatim. source-3 (MLQ): confirms the quoted 'fastest ASIC development cycle for high-performance semiconductors' (verbatim in MLQ's key points), 'went from initial design to manufacturing tape-out in nine months,' engineering samples 'already running machine learning workloads in the lab at production target frequency and power,' '10 gigawatts of OpenAI-designed AI accelerators,' shipping H2 2026 / buildout completing end of 2029, the Brockman 'By designing more of the stack ourselves...' quote, and 'roughly 50% cost savings compared with typical AI GPUs for inference workloads' (verbatim). source-4 (The Decoder): confirms designed-from-scratch (not a modified general-purpose chip), OpenAI design / Broadcom silicon+networking incl. Tomahawk / Celestica integration, self-reported and unverified performance-per-watt claims, technical report to follow, and Microsoft 'expected to buy 40 percent of the chips.'

No fabrications or misattributions found. The ~50% cost-savings figure is cited ONLY to MLQ (correctly single-sourced and attributed to MLQ as reporter). The Microsoft 40% figure is cited ONLY to The Decoder AND explicitly flagged as 'not confirmed across the other sources reviewed' — accurate and appropriately hedged. Unverifiable specifics (3nm/2nm process node, die size, memory, clock, 'reticle-sized') are correctly OMITTED, with the article stating these figures 'were not disclosed in the materials reviewed.' Nine-month design, end-of-2026 deployment, and the 10-gigawatt program all trace to cited sources (MLQ/Constellation/Pulse). The Brockman, Hock Tan, and Richard Ho quotes are verbatim against the snapshots. The internal cross-reference to the GPT-5.3-Codex-Spark/Cerebras article resolves to an existing published article (src/content/articles/2026-02/17-openai-launches-gpt-53-codex-spark-...md), and The Decoder independently confirms that model runs on Cerebras hardware.

High-quality, accurately sourced submission. The automated script returned APPROVE_WITH_CORRECTIONS solely on the non-blocking allowlist warning; after full source verification there is no reader-facing factual error for a corrections record to honestly document, so the verdict is APPROVE. Ready for publication.