Manufacturing
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Micron Breaks Ground on ¥1.5 Trillion Hiroshima Fab Expansion as Japan Pledges Up to ¥500 Billion for AI Memory
Micron broke ground on July 4 on a ¥1.5 trillion ($9.3 billion) expansion of its Hiroshima fab to scale next-generation DRAM and HBM for AI, with Japan's METI pledging up to ¥500 billion in subsidies and equipment installation set to begin in the second half of 2028.
Infineon Opens €5 Billion Smart Power Fab in Dresden, the World's Largest for Power and Analog Chips, Three Months Ahead of Schedule
Infineon opened its €5 billion Smart Power Fab in Dresden on July 2, three months early, doubling its Dresden capacity and adding 1,000 jobs at what it calls the world's largest power-chip factory.
China's Chip-Material Makers Move on Japan's Turf as Guangyuan Commits $1 Billion to T-Glass for AI Servers
Guangyuan is spending $1 billion on T-glass and low-dielectric glass cloth, pushing a Chinese supplier into a niche long dominated by Japan's Nittobo as AI-server demand tightens supply.
Startup Besxar Flies Semiconductor 'Fabships' on Falcon 9 Boosters, Betting the Vacuum of Space Can Make Purer Chip Substrates
Washington startup Besxar is flying microwave-oven-sized 'Fabship' pods on Falcon 9 boosters, the first of 12 SpaceX flights testing whether the vacuum of space can produce purer semiconductor substrates.
SK hynix Commits 100 Trillion Won to Cheongju, Anchored by an 80 Trillion Won M17 NAND Fab, as Korea Doubles Down on AI Memory
SK hynix will spend 100 trillion won ($64.38 billion) on a new NAND fab and advanced packaging plant in Cheongju, part of a 392 trillion won Chungcheong buildout with Samsung.
Nokia to Invest $30 Million Expanding Its Allentown Photonic-Chip Packaging Plant to Feed AI Data Centers
Nokia will spend about $30 million to grow its Allentown, Pennsylvania test and packaging site up to tenfold, backed by state aid and a federal CHIPS tax credit.
Intel's Enhanced 18A-P Process Enters Risk Production, Claiming 9% More Performance and 20-40% Lower Thermal Resistance Than 18A
At the 2026 VLSI Symposium, Intel said 18A-P, a drop-in upgrade to its 18A node, reached risk production with 9% higher performance at iso-power.
ASML, TSMC, and imec Fabricate Complementary 2D-Material Transistors at 50nm Pitch on a Full 300mm Wafer
At the 2026 VLSI Symposium, imec and partners reported MoS2 and WS2/WSe2 transistors at a 50nm contacted poly pitch with 94% of devices operational, a step toward post-silicon logic.
Commerce Awards SandboxAQ $500 Million CHIPS Grant for AI Materials Discovery, Taking a Minority Equity Stake in Return
The U.S. Commerce Department will fund AI-driven work on PFAS-free chemicals, catalysts, rare earth-free magnets, and backup batteries, and take a minority equity stake in return.
Illinois Team Stacks Three Layers of Silicon Transistors at 200°C, Reporting Near-Perfect Yields for Monolithic 3D Chips
A Nature study reports stacking three silicon transistor layers with 98-100% yields using bonding temperatures no higher than 200°C, offering a route to denser chips without smaller transistors.
TSMC Brings Its 'Super Power Rail' Backside Power to VLSI 2026, Claiming Up to 10% More Speed Over N2P as the Angstrom Era's Defining Feature Arrives
At the June 14-18 VLSI Symposium in Honolulu, TSMC details A16 with backside direct-contact power delivery, claiming 8-10% more speed or 15-20% less power versus N2P.
Apple and Intel Reach Preliminary Chip-Manufacturing Deal, Marking the First Partnership Since Apple's 2020 Silicon Switch
Apple and Intel have struck a preliminary agreement for Intel to manufacture some Apple chips, ending a six-year split and handing Intel Foundry its most consequential customer win yet.