TSMC Brings Its 'Super Power Rail' Backside Power to VLSI 2026, Claiming Up to 10% More Speed Over N2P as the Angstrom Era's Defining Feature Arrives

Overview

The defining structural change in leading-edge logic since the move to gate-all-around transistors is finally reaching production silicon at TSMC, and the company chose this week’s industry showcase to lay out the details. At the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits — scheduled for June 14-18, 2026, according to the conference’s own technical tipsheet — TSMC is presenting its A16 process, the first node in which the foundry pairs its nanosheet transistors with a backside power-delivery scheme it calls Super Power Rail.

The symposium, held this year at the Hilton Hawaiian Village in Honolulu, Hawaii, carries the overall theme “Advancing the AI Frontier through VLSI Innovation,” the tipsheet states. A16 is one of the meeting’s headline disclosures, presented as a late-news paper.

What TSMC Disclosed

The A16 paper is listed as Paper T1.5, titled “A16 Angstrom-class CMOS Technology featuring Enhanced Nanosheet Transistors with SuperPower Rail (backside direct contact power delivery) for AI and HPC Applications,” with G. Yeap et al of TSMC credited, according to the VLSI tipsheet. TSMC describes A16 as “their latest GAA technology with backside power delivery solution incorporating a novel backside direct contact – named Super Power Rail (SPR),” the same tipsheet reports.

The headline performance numbers are measured against N2P, TSMC’s performance-enhanced 2nm-class node. Compared with N2P, A16 “provides a further 8%-10% faster speed at the same power, or 15%-20% power improvement and additional 8%-10% chip density gain,” the tipsheet states. Those gains were benchmarked on an ARM core, and the paper reports that A16 “offers up to 10% higher density and faster speed than N2P,” per the figure caption in the tipsheet.

The same figures were flagged ahead of the symposium by TrendForce, which reported that, compared with its performance-enhanced N2P node, A16 “is projected to deliver 8%–10% higher performance at the same power level, or cut power consumption by 15%–20% at equivalent performance, while also improving chip density by an additional 8%–10%.”

On timing, the paper abstract is specific: “Mass production for this A16 is slated for Q4’26,” the tipsheet states.

Why Backside Power Matters

For decades, the metal wires that carry both power and data signals to a chip’s transistors have been stacked above the transistor layer. Backside power delivery splits that scheme in two. As TrendForce explained when TSMC first outlined the approach, “the wires that deliver power to the transistors will be located beneath the transistors instead of above them, known as backside power delivery.” Moving the power network to the back of the wafer relieves congestion on the front-side metal layers, which can then be devoted more fully to signal routing — one reason the technique tends to improve both density and performance at once.

What distinguishes TSMC’s implementation is how the backside network reaches the transistor. TSMC’s A16 “directly connects the power transmission lines to the source and drain, making it more complex than other backside power delivery methods like Intel’s,” according to TrendForce. The source and drain are the points where current enters and exits a transistor; wiring power straight to them shortens the connection and reduces resistance, at the cost of a more intricate manufacturing flow. That “backside direct contact” is the specific feature TSMC has branded Super Power Rail, per the VLSI tipsheet.

The Intel Comparison at the Same Conference

A16 is not the only backside-power disclosure on the VLSI program. Intel is presenting an enhancement to its own 18A family in Paper T1.2, “Intel 18A-P CMOS Technology Enhancement Featuring Advanced RibbonFET (GAA) Transistors and PowerVia for High-Performance Computing,” credited to A. Bowonder et al of Intel Foundry, the tipsheet shows. Intel reports that 18A-P “achieved 9% iso-power performance gain, or over 18% energy efficiency at iso-performance,” according to the tipsheet, with the performance figure measured “~9% iso-power performance gain (at 0.75V) over Intel 18A on an industry standard ARM core sub-block.”

The two presentations make the conference a direct point of comparison between the rival foundries’ angstrom-era roadmaps. TrendForce framed the event as a showdown, noting that Intel’s 18A-P “delivers over 18% lower power at the same performance level, or more than 9% higher performance at equivalent power compared with standard 18A.” The figures are not directly comparable — TSMC measures A16 against N2P, Intel measures 18A-P against base 18A — but both vendors are now leaning on backside power as the lever for their next step in performance-per-watt, and both chose ARM-core workloads as their reference.

Analysis

The significance of A16 is less about any single percentage figure than about what backside power signals for the rest of the decade. Front-side metal routing has become one of the hardest bottlenecks in advanced logic, and moving power delivery to the back of the wafer is the industry’s agreed-upon answer. TSMC’s choice to connect power directly to the transistor’s source and drain — rather than to an intermediate contact — is the more aggressive of the two leading approaches, as TrendForce noted, and the company is betting that the added process complexity pays for itself in efficiency for the AI and high-performance-computing workloads the paper names in its title.

That AI-and-HPC framing is not incidental. The data-center accelerators driving the current build-out are power-limited as much as area-limited, and a 15-20% power reduction at constant performance translates directly into either denser racks or lower operating cost. With the paper abstract stating a Q4’26 mass-production target, the practical question for chip designers is how quickly that headline density and efficiency translate into shipping parts — and whether TSMC’s more complex direct-contact flow yields as cleanly in volume as it does on a benchmark ARM core.

What We Don’t Know

The disclosures summarized in the conference tipsheet are abstracts; the full technical papers presented at the symposium contain detail not reproduced here, and this report does not assert figures beyond those the tipsheet and TrendForce carry. The Q4’26 production date cited here is the schedule stated in the paper abstract; broader roadmap reporting elsewhere has at times described A16 volume timing differently, and the cited sources do not resolve that question. Yield figures, named launch customers, wafer pricing, and the specific products that will adopt A16 are not disclosed in the cited material.