ASML, TSMC, and imec Fabricate Complementary 2D-Material Transistors at 50nm Pitch on a Full 300mm Wafer
At the 2026 VLSI Symposium, imec and partners reported MoS2 and WS2/WSe2 transistors at a 50nm contacted poly pitch with 94% of devices operational, a step toward post-silicon logic.
Overview
The research center imec, working with ASML and TSMC, has reported fabricating complementary transistors built from atomically thin 2D materials at a 50-nanometre contacted poly pitch on a full 300mm wafer, with 94 percent of the devices operational. The result, presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, marks a step in moving 2D-channel transistors out of single-device lab demonstrations and toward the kind of integration that volume manufacturing requires, according to imec.
For decades, transistor scaling has relied on shrinking silicon features. As channel lengths approach a few nanometres, silicon’s electrostatics degrade, and the industry has long looked to alternative channel materials. Transition metal dichalcogenides (TMDs) — atomically thin semiconductors such as molybdenum disulfide — are among the leading candidates, but demonstrating them at competitive dimensions on industry-standard wafers has remained a barrier.
What We Know
The team integrated both transistor polarities on the same 300mm wafer. The n-type FETs use MoS2 as the channel material, while the p-type FETs use either WS2 or WSe2, according to imec. Having both n- and pFETs on the same wafer is what enables CMOS-like logic, the foundation of modern digital chips. The same materials and the dual-polarity integration were confirmed by Bits&Chips and Semiconductor Today.
The headline metric is the 50nm contacted poly pitch (CPP), a measure that combines the gate length and the source/drain contact length. Imec stated that “with 94% operational transistors (i.e., with Imax/Imin >105), the CMOS-like integration approach – with n- and pFETs integrated on the same 300mm wafer – is proven to be robust and stable,” per the imec release. The 94 percent operational figure and the Imax/Imin ratio greater than 10^5 were also reported by Semiconductor Today.
EUV lithography was central to reaching those dimensions. Gouri Sankar Kar, VP R&D compute and memory device technologies at imec, said: “For the first time, we achieved 50nm CPP – a metric determined by both the gate length and source/drain contact length – without affecting the performance of the 2D n and pFETs. The use of single-patterning EUV lithography, optimized in close collaboration with ASML, was key in enabling the scaled CPP,” as quoted by imec.
The sharper resolution of EUV also allowed shorter channels than earlier 300mm 2D demonstrations. Etienne De Poortere, Director Technology Development Center Europe of ASML, said: “2D TMD materials could potentially enable much smaller and higher-performance transistors than those based on silicon, but 2D-channel devices that have been demonstrated so far using 300mm processes are actually fairly large, and patterned using older lithographic technologies. Thanks to the much sharper resolution of EUV lithography, we were able to create TMD transistors with channel lengths as small as 28 nm, and at a pitch compatible with the most advanced transistor nodes,” according to imec. The 28nm channel length was likewise reported by Bits&Chips.
A key part of the result is the fabrication approach. Kar attributed the device behavior to “the use of an innovative ‘reverse’ thin-film transistor (TFT) fabrication flow,” per imec. Bits&Chips described the architecture as using pre-patterned tungsten bottom contacts, with the 2D channel material then covered by an overlapping deposited gate.
Imec frames the work as relevant to several applications beyond conventional front-end logic. The devices are envisioned for ultra-scaled logic, back-end-of-line, and wafer backside applications, according to Semiconductor Today. The symposium itself ran June 14 to 18 in Honolulu, Hawaii, per Semiconductor Today.
What We Don’t Know
The announcement is a research milestone, not a production qualification. The sources do not give a timeline for when 2D-material transistors might appear in a commercial process node, nor do they specify drive-current or performance figures benchmarked against current silicon nodes in a directly comparable form. Yield at the 94 percent level for individual devices is a different and earlier-stage measure than the defect densities required for high-volume manufacturing of complete circuits. It also remains unstated which, if any, future foundry node would adopt the approach.
Analysis
The collaboration pairs the three actors that would each need to participate for 2D channels to reach manufacturing: a foundry (TSMC), the dominant lithography equipment supplier (ASML), and the research institute that has long served as a shared proving ground for the industry (imec). Dr. Min Cao, TSMC’s Vice President and CTO, said “our research collaboration is instrumental in pushing the boundaries of semiconductor innovation,” as quoted by imec.
The emphasis on a 300mm wafer and on a pitch “compatible with the most advanced transistor nodes” is the signal worth noting. Many prior 2D-transistor results have been single devices or small arrays on research substrates; demonstrating both polarities together, at an advanced pitch, on a production-format wafer is the kind of integration step that determines whether a material ever escapes the laboratory. The work follows imec’s broader push into sub-2nm research infrastructure, including its NanoIC pilot line, which The Machine Herald previously reported on earlier this year.
Whether 2D-material transistors ultimately supplement silicon — in back-end or backside roles — or eventually replace it in the channel remains an open question that this result does not settle. What it does establish is that the lab-to-fab gap for these materials has narrowed at the dimensions that matter.