Intel Foundry Nears Billion-Dollar Advanced Packaging Deals with Google and Amazon as EMIB Gains Ground Against TSMC
Intel is in advanced talks with Google and Amazon for EMIB-based chip packaging services worth billions annually, positioning its foundry division as a credible alternative to TSMC's constrained CoWoS capacity.
Overview
Intel is reportedly in advanced negotiations with Google and Amazon to provide chip packaging services for their custom AI processors, according to Tom’s Hardware. The discussions center on Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology, with potential customer commitments expected in the second half of 2026. If the deals close, they would represent Intel Foundry’s first major external packaging wins and a meaningful challenge to TSMC’s dominance in advanced packaging for AI accelerators.
What We Know
Both Google and Amazon design custom AI chips — Google’s Tensor Processing Units and Amazon’s Trainium and Inferentia accelerators — but rely on third-party foundries and packaging houses for manufacturing. Intel’s EMIB-T, the next generation of its silicon bridge technology that adds through-silicon vias for improved power delivery and signal integrity, is expected to become available to external customers later this year, according to Tom’s Hardware.
Intel CFO David Zinsner signaled the scale of the opportunity at a Morgan Stanley event in early March, stating that the company is “close to closing some deals that are in the billions of dollars per year” in packaging revenue, as reported by The Register. Zinsner described packaging as the most promising near-term revenue stream for the foundry division, noting strong customer engagement and revising earlier projections from hundreds of millions to “well north of $1 billion” annually.
Intel’s packaging portfolio extends beyond EMIB. The company recently announced EMIB-T alongside two new additions to its Foveros 3D stacking architecture — Foveros-R and Foveros-B — at an industry event where it also formalized a new engagement with Amkor Technology, as detailed on the Intel Newsroom. Amkor’s Songdo K5 facility in South Korea is now producing EMIB packages for Intel, marking the first time the company has outsourced this technology.
Why It Matters
The timing reflects a structural constraint in the AI chip supply chain. TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging capacity has been a bottleneck for hyperscalers since 2024, with the Taiwanese foundry scrambling to scale monthly output from approximately 80,000 wafers to a target of 130,000 by late 2026. NVIDIA reportedly holds over 60 percent of TSMC’s total CoWoS allocation, leaving limited room for other customers designing custom silicon.
Intel’s EMIB takes a fundamentally different architectural approach. Rather than using a large monolithic silicon interposer to connect chiplets — the basis of TSMC’s CoWoS — EMIB embeds small silicon bridges directly in the package substrate, connecting adjacent dies with high-density interconnects. This approach avoids the yield challenges and cost scaling issues of large interposers, and Intel has stated that the bridge count can scale without increasing substrate complexity.
The geographic dimension is also significant. TSMC’s advanced packaging operations are concentrated almost entirely in Taiwan, while Intel offers packaging capacity across the United States, Malaysia, and through its Amkor partnership in South Korea. For hyperscalers navigating supply chain diversification mandates, a domestic or geographically distributed packaging option carries strategic value beyond pure cost or performance comparisons.
What We Don’t Know
Neither Google nor Amazon has publicly confirmed packaging discussions with Intel. The specific technical requirements under negotiation — including package sizes, chiplet counts, and memory stack configurations — remain undisclosed. It is also unclear whether the hyperscalers would shift existing designs from TSMC’s CoWoS to Intel’s EMIB or develop new chip architectures specifically targeting Intel’s packaging capabilities.
Intel has indicated that its foundry division expects to reach breakeven operating margins by the end of 2027, as noted by The Register. Whether packaging revenue alone can materially accelerate that timeline depends on the margin profile of these deals. Zinsner has suggested gross margins around 40 percent for packaging services, but final contract terms have not been disclosed.
The competitive response from TSMC also remains an open question. TSMC is constructing an advanced packaging facility in the United States, with operations expected between late 2027 and 2028, which could eventually address the geographic diversification concerns that currently favor Intel.
Analysis
Intel’s advanced packaging push represents a pragmatic pivot for a foundry business that has struggled to win external wafer manufacturing customers. Packaging services have a shorter qualification cycle than leading-edge transistor fabrication, and Intel’s EMIB technology is already proven in its own products, including Ponte Vecchio and Meteor Lake processors. By leading with packaging rather than waiting for 18A process node wins, Intel can generate revenue and build customer relationships that may eventually expand into full foundry engagements.
The broader implication is that advanced packaging is emerging as a competitive domain in its own right, separate from transistor-level process technology. As AI accelerator architectures increasingly rely on chiplet disaggregation and high-bandwidth memory stacking, the entity that controls packaging capacity holds significant leverage over the AI hardware supply chain. Intel’s bid to capture a share of this market from TSMC could reshape the foundry landscape if the reported deals with Google and Amazon materialize in the second half of 2026.