ASML Looks Beyond Its EUV Monopoly, Plans Advanced Packaging and Larger-Die Tools for the AI Chip Era
ASML's CTO reveals plans to build packaging, bonding, and inspection tools that move the company beyond EUV lithography and into the broader AI semiconductor supply chain.
Overview
ASML Holding, the Dutch company whose extreme ultraviolet (EUV) lithography machines are indispensable to every leading-edge chipmaker, is plotting a strategic expansion that could reshape its role in the semiconductor industry. In an exclusive interview with Reuters, Chief Technology Officer Marco Pieters disclosed that the company is developing tools for advanced chip packaging, bonding, and inspection — stepping well beyond the lithography niche that has made it a $560 billion company.
The move reflects a broader shift in AI chip architecture, where performance gains increasingly depend not on shrinking transistors alone but on how multiple specialized chiplets are stacked, interconnected, and packaged together.
What We Know
Pieters told Reuters that the company is thinking in 10- to 15-year time horizons. “We look, not just for the next five years, we look at the next 10, maybe 15 years,” he said, describing research into “what are potential directions the industry could take, and what would it require in terms of packaging, bonding, etc.”
The first product signaling this diversification already shipped in late 2025: the TWINSCAN XT:260 scanner, designed specifically for advanced packaging lithography. According to Tom’s Hardware, the XT:260 delivers 400 nm resolution with a 35 nm overlay and can process up to 270 wafers per hour — roughly four times the throughput of existing tools used for packaging lithography. It handles thick or warped wafers and is optimized for technologies like Intel’s Foveros, TSMC’s CoWoS (Chip-on-Wafer-on-Substrate), and System-on-Integrated-Chips architectures.
Beyond packaging, ASML engineers are also investigating whether the company can print larger silicon dies than the current postage-stamp-sized limit that constrains chipmaking speed, according to Reuters. Pieters also confirmed that AI will be embedded into the company’s control software and inspection workflows across both new and legacy product lines.
Pieters, who took over as CTO in October after a 40-year tenure by Martin van den Brink, brings a software development background to the role. He described the integration of AI into ASML’s tools as something happening “as we speak,” with engineers exploring additional scanner systems for stacked chip configurations.
Why It Matters
For decades, ASML’s business model has been defined by a single, extraordinarily valuable product: EUV lithography equipment. The company is the sole supplier of these machines, each costing hundreds of millions of dollars, and its next-generation High-NA EUV tools carry a price tag of approximately $400 million per unit, as Reuters reported in a separate piece. TSMC and Intel are early adopters of the High-NA systems, and ASML has disclosed that its High-NA tools have already processed 500,000 wafers and achieved 80 percent uptime.
But the architecture of AI chips is evolving in ways that make packaging as important as lithography. Modern AI processors, including NVIDIA’s flagship GPUs, increasingly rely on chiplet designs where multiple specialized dies are stacked vertically and connected via nanoscale interconnects. TSMC’s CoWoS advanced packaging capacity has become a bottleneck so severe that Alphabet reportedly reduced its 2026 TPU production targets due to limited access, according to industry analysts.
This shift has elevated packaging from what was traditionally a low-margin, high-volume commodity step into a higher-margin manufacturing segment where precision matters. ASML sees an opportunity to apply its lithography expertise — particularly in alignment accuracy and overlay control — to this adjacent market.
What We Don’t Know
ASML has not disclosed specific timelines for when its next packaging tools beyond the XT:260 will reach production. Most of the work Pieters described remains in early research phases, and equipment qualification at chipmaker facilities typically takes years. The company has also not provided revenue projections for its packaging business or detailed how it will differentiate against established packaging equipment suppliers such as Applied Materials and Tokyo Electron.
Whether ASML can successfully break the current die-size limitation — a constraint imposed by the physics of its optical systems — remains an open technical question. The company has not specified what approach it would take or how such a change would affect throughput and cost.
Analysis
ASML’s expansion into packaging tools represents a calculated bet that the semiconductor industry’s center of gravity is shifting. As transistor scaling slows and chiplet architectures proliferate, the value in chip manufacturing is migrating from the front-end lithography step toward the back-end assembly and packaging processes that determine how fast disparate dies can communicate.
The timing is notable. ASML’s stock trades at roughly 40 times forward earnings — a valuation that prices in continued dominance in lithography but leaves little room for growth if EUV demand plateaus. By positioning itself in the estimated $40 billion to $50 billion annual advanced packaging equipment market, the company could diversify its revenue streams while leveraging core competencies in precision optics and wafer handling.
Still, entering packaging puts ASML into competition with entrenched players who have decades of process expertise. The company’s success will likely hinge on whether its lithography-grade precision offers a meaningful advantage in packaging workflows that have historically tolerated coarser specifications. The XT:260’s four-fold throughput improvement over incumbent i-line steppers suggests ASML believes the answer is yes.