TSMC Unveils 2029 Roadmap at Annual Symposium: A13, A12, and N2U Announced as A16 Slips to 2027
TSMC debuted its A13 and A12 process nodes and updated its full roadmap through 2029 at its North America Technology Symposium, while confirming A16 volume production slides to 2027.
Overview
TSMC used its annual North America Technology Symposium in Santa Clara on April 23, 2026, to lay out its most detailed public roadmap in years. Under the theme “Expanding AI with Leadership Silicon,” the company debuted A13 — a 2029-target process node — alongside the previously unannounced A12 platform, updated its N2 family with a new N2U variant, and formally confirmed that its A16 node will not reach volume production until 2027, a one-year slip from prior guidance. The disclosures arrive as TSMC’s AI business has become the fastest-growing segment of a company already posting record revenues, with AI-related high-performance computing generating approximately $11.1 billion in Q1 2026 alone, according to Next Platform.
What We Know
A13: An Optical Shrink of A14 for 2029
A13 is a direct optical reduction of the A14 process, shrinking linear dimensions by approximately 3 percent and delivering a roughly 6 percent reduction in chip area compared to A14, according to TrendForce’s coverage of the symposium. Critically, A13 maintains full electrical and design-rule compatibility with A14, meaning chip designers can migrate existing A14 layouts to A13 without starting from scratch. The node targets AI accelerators, high-performance computing, and mobile applications, and is scheduled for volume production in 2029. Notably, A13 will not require High-NA EUV lithography tools — a deliberate strategic choice that diverges from Intel’s roadmap and potentially affects ASML’s near-term High-NA revenue projections, as noted by TrendForce.
A12: Backside Power Delivery Arrives in 2029
A12 represents a more significant architectural advance. It introduces second-generation nanosheet gate-all-around (GAA) transistors alongside TSMC’s NanoFlex Pro technology and a Super Power Rail (SPR) backside power delivery network, per New Electronics. Backside power delivery routes the power grid beneath the transistor layer rather than sharing routing resources with signal wires above, freeing die area and improving voltage delivery to densely packed logic. A12 is positioned as the successor to A16 in the high-performance data-center segment and is also scheduled for 2029 production.
N2U: A Cheaper On-Ramp for Existing N2 Designs
The N2U variant, targeting 2028 production, is designed as a cost-effective upgrade path for customers already on the N2 platform. It delivers 3–4 percent higher performance at the same power, or 8–10 percent lower power at equivalent speed, plus a modest 2–3 percent logic density improvement versus N2P — all while maintaining IP compatibility with existing N2 designs, according to TechSoda’s symposium coverage. A separate N2A (automotive-grade) variant was also announced, featuring nanosheet transistors and targeting AEC-Q100 certification in 2028, with 15–20 percent speed gains versus the prior N3A automotive node.
A16 Slips to 2027
The most market-moving disclosure may be A16’s confirmed delay. TSMC had previously indicated A16 — its 1.6nm-class node incorporating SPR backside power delivery on a first-generation nanosheet GAA architecture — would reach volume production in late 2026. At the symposium, the company confirmed the timeline has shifted to 2027, as reported by TrendForce. TSMC’s explanation, according to TrendForce reporting, was that “actual product ramp depends on customers, and we expect volume production to begin in 2027.”
Advanced Packaging Expansion
Beyond transistor-level nodes, TSMC announced significant CoWoS packaging expansions. By 2028, CoWoS interposers will scale from 5.5 times to 14 times the reticle size and will be capable of integrating approximately 10 compute dies alongside 20 HBM memory stacks on a single substrate, according to Focus Taiwan’s symposium coverage. COUPE, its co-packaged optics platform combining silicon photonics with logic dies, entered mass production in 2026 and is claimed to double power efficiency while reducing data-transmission latency by 90 percent.
CEO Statement
TSMC Chairman and CEO C.C. Wei stated at the symposium: “TSMC’s advanced process technologies lead the industry in density, performance, and power efficiency, and we continually strive to make them even better for our customers’ future products, ensuring customers’ success as their most reliable technological partner,” per TechSoda.
What We Don’t Know
Several important details remain undisclosed. TSMC has not named specific customers committing to A13 or A12, and it is not known whether Apple, NVIDIA, AMD, or other anchor customers have already signed design-start agreements for 2029 nodes. The precise cause of the A16 delay — whether it is a yield challenge, a customer readiness issue, or a deliberate pacing decision — has not been publicly clarified beyond the customer-alignment explanation. TSMC also has not confirmed the pricing differential between A13 and A12, or whether the two 2029 nodes are intended to serve distinct market tiers in the way N3P and N3E serve different performance-cost trade-offs on the N3 platform. The competitive implications of skipping High-NA EUV through 2029 remain an open question, particularly given that Samsung Foundry and Intel both plan to adopt the technology earlier.
Analysis
The symposium roadmap reflects TSMC’s consistent strategy of offering incremental “shrink” nodes alongside full-node advances, giving customers a choice between lower migration risk and higher performance gains. A13, as a compatibility-preserving optical reduction of A14, lowers the barrier for customers to capture density improvements without a full redesign — a meaningful advantage when chip design costs at leading-edge nodes can exceed $500 million. A12, with its backside power delivery and advanced nanosheet transistors, represents the true generational leap for data-center and AI applications.
The A16 slip is notable but not disruptive in isolation: the node remains on track, and 2027 volume production is still ahead of when most customer products would require it. More significant is the company’s explicit confirmation that neither A13 nor A12 will require High-NA EUV, a decision that keeps TSMC on proven deep-UV and standard EUV tooling for another generation. That choice has direct financial consequences for ASML, whose High-NA NXE:3600D systems carry price tags reportedly exceeding $380 million each. TSMC’s decision to extend standard EUV — rather than pull High-NA demand forward — suggests the foundry believes existing tooling remains cost-competitive at the density levels AI chip customers currently require.
For context on the scale of TSMC’s AI-driven growth, the company in 2025 served 534 customers across 12,682 distinct products with 305 process technologies, according to TechSoda. Its AI chip revenues grew from $1.52 billion in 2022 to $33.38 billion in 2025, per Next Platform. The 2029 roadmap is, in part, a statement of confidence that this demand trajectory will remain intact long enough to justify committing to process nodes three years out.