Intel's Enhanced 18A-P Process Enters Risk Production, Claiming 9% More Performance and 20-40% Lower Thermal Resistance Than 18A
At the 2026 VLSI Symposium, Intel said 18A-P, a drop-in upgrade to its 18A node, reached risk production with 9% higher performance at iso-power.
Overview
Intel said its performance-enhanced 18A-P manufacturing process has entered risk production, an early stage that runs a limited number of wafers to validate a node before high-volume production. The company disclosed the milestone at the 2026 VLSI Symposium on June 16, 2026, in Santa Clara, California, describing 18A-P as “the first performance enhancement in the Intel 18A family” and saying it had reached the stage “meeting the timeline first shared with customers and partners last year,” according to Intel Newsroom.
The announcement matters because Intel is leaning on its Foundry business and the 18A family to re-establish itself at the leading edge of chip manufacturing, where it competes with TSMC and Samsung. 18A-P is positioned not as a brand-new node but as a refined version of 18A that existing designs can move onto with minimal rework.
What We Know
Intel says 18A-P “delivers 9% higher performance at iso-power or 18% lower power at iso-performance compared to Intel 18A,” per Intel Newsroom. In plainer terms, a chip drawing the same power can run up to 9% faster, or run at the same speed while consuming 18% less power. igor’sLAB independently described the same figures, noting that “at the same power draw, a design should be able to operate up to nine percent faster” and that “at the same speed, energy consumption should in contrast fall by 18 percent.”
The node also targets thermal and interconnect gains. Intel cites “20-40% improved thermal resistance through both materials and design innovations” and “10-30% improved via resistance” from geometric and materials optimizations, according to Intel Newsroom. The thermal figure was corroborated by Benzinga, which reported “a 20% to 40% improvement in thermal resistance,” and by igor’sLAB, which put the via-resistance improvement at “ten to 30 percent.”
The headline transistor-level addition is what Intel calls Power Boost. The company describes it as “Intel 18A-P’s new dual contact, low resistance transistor option enabling increased drive current and greater frequency at matched capacitance,” per Intel Newsroom. igor’sLAB characterized the approach as a transistor “with two particularly low-resistance contacts” intended “to enable higher drive current and thus higher frequencies.”
Intel is emphasizing continuity with 18A rather than a clean break. The company says 18A-P “is fully design rule compatible with Intel 18A, enabling straightforward reuse of existing IP and design flows,” according to Intel Newsroom. igor’sLAB called this “the most strategically important point,” noting that companies “that have already prepared IP blocks or designs for 18A are intended to be able to continue using them on 18A-P.” Geometrically, the two share the same dimensions: Intel says 18A-P “offers two cell heights (180nm and 160nm), a contacted poly pitch of 50nm,” per Intel Newsroom. Both nodes are built on Intel’s RibbonFET gate-all-around transistors and PowerVia backside power delivery.
Naga Chandrasekaran, executive vice president and general manager of Intel Foundry, framed the VLSI disclosures as a signal of commitment. “Our updates and presentations at VLSI signal to Intel Foundry customers and partners that we are fully committed to leading edge process innovation over the long term,” he said, according to Intel Newsroom and Benzinga.
Investors reacted positively to the news. Benzinga reported that “Intel shares were up 3.99% at $121.72 during premarket trading on Wednesday.”
18A-P is intended to carry future products. Intel has already said its Diamond Rapids Xeon 7 server processor, due in 2027, will be built on 18A-P, as previously reported.
What We Don’t Know
Risk production is not volume production. Intel did not disclose a date for when 18A-P moves to high-volume manufacturing, nor did it publish yield figures for the node. The company also did not announce specific external foundry customers committed to 18A-P at the symposium. Intel’s broader roadmap items mentioned at VLSI — including CFET, GaN-and-silicon integration, and ruthenium interconnect — were presented as long-term research directions without production timelines, per Intel Newsroom.
Analysis
The market’s open question is less about 18A-P’s specifications than about Intel’s ability to win outside customers and hit competitive yields. Some Wall Street voices remain unconvinced about the timeline for Intel to seriously challenge TSMC. BigGo Finance reported that commentator Jim Cramer said he is “very, very skeptical” about Intel matching TSMC and doubted that goal could be achieved before 2028.
Yield is the recurring concern. Counterpoint Research’s Neil Shah told BigGo Finance that “if they can achieve over 90% yield in the first month of volume production, I think they can attract more customers.” The same report noted that revenue from external foundry customers “totaled just $174 million, accounting for roughly 3% of total foundry revenue,” and that Intel’s next-generation 14A process is “expected to begin risk production in 2028 and enter volume manufacturing in 2029.”
For now, 18A-P’s design-rule compatibility is the most pragmatic part of the story. By making the enhanced node a drop-in upgrade rather than a fresh migration, Intel lowers the cost and risk for any team already targeting 18A — including its own data center roadmap — to capture the extra performance and efficiency without redesigning their chips.