Provenance Record

Well-structured News piece (840 words, within the 400-1200 News range). Overview/What We Know/What We Don't Know/Analysis sections cleanly separate Intel's announcement from open questions and external skepticism. Technical depth is appropriate and accurate.

All 4 source snapshots read from disk and verified. source-0 (Intel Newsroom, primary, status 200): confirms VERBATIM the 9% higher performance at iso-power / 18% lower power at iso-performance, 20-40% improved thermal resistance, 10-30% improved via resistance, Power Boost 'dual contact, low resistance transistor option,' full design-rule compatibility, two cell heights (180nm and 160nm), 50nm contacted poly pitch, RibbonFET + PowerVia, 'first performance enhancement in the Intel 18A family,' risk production 'meeting the timeline first shared with customers and partners last year,' Santa Clara June 16 2026, and the CFET/ruthenium/GaN roadmap items. The Chandrasekaran quote ('Our updates and presentations at VLSI signal to Intel Foundry customers and partners that we are fully committed to leading edge process innovation over the long term') is verbatim in both Intel Newsroom and Benzinga. source-1 (igor'sLAB, 200): confirms 'nine percent faster,' 'fall by 18 percent,' via resistance 'ten to 30 percent,' 'two particularly low-resistance contacts,' 'higher drive current,' 'most strategically important point,' 'prepared IP blocks' — all verbatim. source-2 (Benzinga, 200): confirms '20% to 40% improvement in thermal resistance' and 'up 3.99% at $121.72 during premarket trading on Wednesday' — verbatim. source-3 (BigGo Finance, 200): confirms Cramer 'very, very skeptical' about the 2028 timeline, Neil Shah / Counterpoint Research 'over 90% yield in the first month of volume production,' '$174 million' external foundry revenue 'roughly 3% of total foundry revenue,' and 14A 'risk production in 2028 and enter volume manufacturing in 2029' — all verbatim.

Rule 9 satisfied: every disputed process specific (9%/18%, 20-40% thermal, 10-30% via, Power Boost, 50nm CPP, design-rule compatibility, June 16 2026 VLSI, risk production) is attributed to Intel as the source's own claim — phrased 'Intel says,' 'Intel cites,' 'The company describes,' 'according to Intel Newsroom' — never presented as independently validated. igor'sLAB corroboration is labeled as an independent restatement of the same Intel figures, which the snapshot supports. No hallucinated numbers, names, or dates.

APPROVE. Integrity checks all pass (signature valid, hash valid). All four sources personally read and verified; every quote, number, name, and date traces to its cited source. Analyst skepticism (Cramer, Shah via BigGo Finance) is correctly confined to the Analysis section and kept out of the headline and lead. No paywalled/403/404 outlets (Tom's Hardware, TechTimes, HotHardware) are cited. The only finding is a non-blocking allowlist warning for igorslab.de, benzinga.com, and finance.biggo.com — noted in recommendations; the allowlist file was not modified.