Illinois Team Stacks Three Layers of Silicon Transistors at 200°C, Reporting Near-Perfect Yields for Monolithic 3D Chips

Overview

A team at the University of Illinois Urbana-Champaign has demonstrated a way to build silicon transistors in vertical layers stacked directly on top of one another, reporting near-perfect device yields while keeping the manufacturing temperature low enough to leave the underlying circuits intact. The work was published in the journal Nature on May 27, 2026, under the title “Monolithic three-dimensional integration of silicon transistors”.

The approach speaks to one of the most persistent questions in the chip industry: how to keep increasing computing density when shrinking individual transistors is growing harder and more expensive. Rather than packing more devices onto a single flat surface, the Illinois process builds upward.

What We Know

The researchers fabricated three stacked layers of silicon circuitry, each layer containing 625 transistors, and reported device yields between 98 and 100 percent, according to the University of Illinois Grainger Engineering. The same figures are reported by Interesting Engineering and SciTechDaily.

The central obstacle the work addresses is thermal. Standard silicon processing can approach 1,000 degrees Celsius, but once the first layer of circuits is finished, the heat used to build any additional layers has to stay low enough not to damage what is already there. The industry generally treats 400 degrees Celsius as the thermal budget limit for those additional layers, according to the University of Illinois. The new bonding process operates at temperatures no higher than 200 degrees Celsius, as reported by Interesting Engineering and SciTechDaily.

To stay within that budget, the team transferred ultrathin single-crystalline silicon nanomembranes onto completed circuit layers and used junctionless transistors to avoid the high-temperature doping steps that normally accompany transistor fabrication, according to Interesting Engineering. The Nature abstract describes the membranes as “uniformly doped, ultrathin (≤10 nm) single-crystalline silicon nanomembranes” that “can be vertically stacked,” and reports building “logic gates, including inverters, NAND, NOR gates and static random-access memory cells, based on up to three-tier integration,” according to the paper in Nature.

Because the layers sit so close together, the vertical connections between them can be far denser than the wafer-bonding methods used in much of today’s 3D packaging. The interlayer connections are 10 to 100 times denser than wafer bonding, according to the University of Illinois and SciTechDaily. The stacked transistors also delivered output current densities three to four times greater than monolithic devices made from alternative materials, according to the University of Illinois and SciTechDaily.

Qing Cao, described by Interesting Engineering as an associate professor of materials science and engineering at the University of Illinois Urbana-Champaign, framed the motivation in terms of physical limits. “In a sense, we’re hitting a limit imposed by physics…we have to start thinking beyond just squeezing more devices on a single surface,” Cao said, according to SciTechDaily. Describing the payoff of going vertical, Cao told the University of Illinois that “It’s like replacing a sprawling suburb with high-rises.”

The density argument is concrete in memory. Cao noted that today it takes six transistors on a single plane to store one bit of information, and that vertical integration lets those devices be distributed across multiple layers instead, according to the University of Illinois and SciTechDaily. On the broader benefit, Cao told Interesting Engineering that “you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient.”

The paper lists authors Bao Lam, Yung Man Yu, Hyunjun Nam, Hsu-Chih Ni, Shomik Chatterjee, Shaloo Rakheja, Jian-Min Zuo, and Qing Cao, according to the paper in Nature. The work was carried out through the Center for Advanced Semiconductor Chips with Accelerated Performance, whose industry partners include IBM, Intel, and Taiwan Semiconductor Manufacturing Company, according to the University of Illinois and SciTechDaily.

What We Don’t Know

The demonstration is a laboratory result, not a manufacturing process. Cao said the layers can be stacked beyond the three demonstrated and still yield high-performing transistors, but the paper itself frames the approach as particularly suited to research and low-volume prototype development rather than mass production, according to the paper in Nature.

There are also open engineering questions. Interesting Engineering notes that higher-than-normal voltages are required to power the chips, a limitation that would need to be addressed before commercial deployment, according to Interesting Engineering. Neither the press materials nor the abstract commit to a timeline for transferring the technique to commercial foundries, and the presence of IBM, Intel, and TSMC as partners indicates interest rather than a product roadmap.

Analysis

The result sits at the intersection of two trends the chip industry has been navigating for years: the rising cost and difficulty of shrinking transistors further, and the growing reliance on stacking and packaging to deliver density gains instead. Cao observed that vertical integration is already starting to appear in commercial devices, particularly in specialized AI hardware, according to Interesting Engineering.

What distinguishes this work from much of the 3D integration already in production is granularity. Where wafer-bonding and packaging approaches join completed dies, the Illinois process builds device layers sequentially on the same substrate, allowing the much denser interlayer connections the team reported. If the low-temperature, junctionless approach holds up at larger scales and the voltage limitation can be resolved, monolithic 3D integration using standard single-crystalline silicon would give designers another axis to grow along — upward — without depending on ever-smaller features. For now, the demonstration establishes that near-perfect yields are achievable within the industry’s thermal constraints, which is the precondition any commercial path would have to meet first.