Samsung Unveils First HBM5 Mockup at Computex 2026, Putting Thermal Management at the Center of the Next AI Memory Race

Overview

Samsung used Computex 2026 in Taipei to show a physical mockup of its eighth-generation high-bandwidth memory, HBM5, for the first time, pairing it with a new in-package cooling structure, according to Tom’s Hardware. The disclosure was modest in form — a mockup rather than a shipping product — but its substance points to where the contest for AI memory is heading: as much toward managing heat as toward raw speed.

The details Samsung shared, alongside a competing thermal approach unveiled by rival SK hynix, frame the next memory generation around stability and cooling at the interface between the memory stack and the processor it feeds.

What We Know

Samsung is preparing HBM5 in 12-layer, 16-layer, and 20-layer DRAM stack configurations, TrendForce reported. Taller stacks pack more memory into the same footprint but concentrate more heat — the problem the company’s accompanying thermal work is meant to address.

At the center of that work is a structure Samsung calls Heat Path Block (HPB). Rather than letting heat escape outward through the core dies, HPB “builds a separate set of thermal pillars that pull heat from inside the stack and carry it to a spreader sitting above or beside the package,” according to Tom’s Hardware. TrendForce described HPB as featuring “an independent thermal path within the D2D PHY region.”

That region is where the heat is worst. The design “concentrates on the D2D PHY layer, the high-speed link between the HBM base die and the GPU, where power density and temperatures increase exponentially,” Tom’s Hardware reported.

The other notable disclosure concerns manufacturing. Samsung confirmed it will fabricate HBM5’s base die on its in-house 2nm process, “down from the 4nm node used for HBM4 and HBM4E,” Tom’s Hardware reported. A more advanced base-die process is aimed at improving processing efficiency in the layer that links the memory to the accelerator.

None of this is imminent. Mass production of HBM5 is expected around 2028, according to TrendForce. Tom’s Hardware similarly reported that neither Samsung’s Heat Path Block method nor SK hynix’s competing approach is expected to reach mass production before 2028, noting that both are slated to debut with HBM5.

The Competitive Backdrop

Samsung’s HBM5 preview lands as SK hynix pushes its own thermal answer aimed at the same interface. SK hynix’s iHBM architecture “uses cooling elements made of electrically non-conductive, thermally conductive silicon into the D2D PHY layer, which the company said cuts thermal resistance by more than 30% against current products,” Tom’s Hardware reported. SK hynix plans to apply iHBM “from next-generation products, such as HBM5,” the same report said.

The convergence is striking: both memory makers are targeting the D2D PHY layer — the die-to-die physical interface between the memory and the processor — as the chokepoint that determines how tall stacks can grow and how fast they can run before thermal throttling sets in.

What We Don’t Know

Samsung disclosed the HBM5 stack options, base-die process, and thermal design, but several specifics remain open. The mockup is not a finished product, and Samsung has not detailed final per-stack capacity or bandwidth figures for HBM5. The roughly 2028 production window is described as an expectation rather than a committed ship date. And the relative effectiveness of Samsung’s Heat Path Block against SK hynix’s iHBM — both aimed at the D2D PHY interface — will not be clear until parts are sampling against real AI accelerators. Whether the move to a 2nm base die delivers the efficiency Samsung is targeting is likewise a question for the foundry’s execution between now and mass production.