Provenance Record

Well-structured News piece with clear Overview / What We Know / What We Don't Know / Analysis sections. Technical depth is appropriate — the four-generation roadmap (Aïdôs, Zélos, Styx, Panopeia) is presented with precise qubit counts, logical error rate targets, and architectural context. The author properly separates company targets from achieved performance, and the 'What We Don't Know' section candidly notes that C12 has not disclosed two-qubit gate fidelities, physical error rates, or fresh funding attached to the roadmap.

{"https://thequantuminsider.com/2026/04/17/c12-unveils-roadmap-targets-useful-fault-tolerant-quantum-computing-by-2033/":"VERIFIED — Confirms all four generation specifications: Aïdôs (2027, 16 physical qubits, 1 logical, sub-microsecond gate speeds), Zélos (2030, 236 physical / 8 logical, ~10⁻⁵ error rate, chiplet packaging + cryogenic electronics + all-digital control + on-chip bias array + multiplexed readout), Styx (2032, 8,500 physical / 128+ logical, 10⁻⁶), Panopeia (2033, 100,000+ physical / ~800 logical, ~10⁻⁷, 17-square-meter footprint, sub-watt per qubit, single cryostat). Both Desjardins quotes verbatim: Pierre ('real challenge is building quantum computers that can scale reliably') and Matthieu ('design systems where quantum error correction and large-scale integration are efficient at scale'). Superconducting bus + chiplet 3D integration claims supported.","https://thequantuminsider.com/2026/03/16/c12-partners-qc-design-plaquette-fault-tolerant-quantum-computing-carbon-nanotubes/":"VERIFIED — Confirms carbon-12 isotopically purified nanotubes suspended above silicon chips, 'two orders of magnitude larger than previously measured in carbon-based quantum circuits' coherence time quote verbatim, QC Design Plaquette partnership for QLDPC code benchmarking against C12's high-connectivity architecture, and hardware imperfection simulation — all as cited.","https://siliconangle.com/2024/06/19/french-quantum-computing-startup-c12-raises-18m-stabilize-qubits-carbon-nanotubes/":"VERIFIED — Confirms €18 million (~$19.4 million) pre-Series A in June 2024 led by Varsity Capital, European Innovation Council Fund, and Verve Ventures, with 360 Capital, Bpifrance, and BNP Paribas Développement participating. Nano-assembly process for integrating nanotubes onto silicon chips is described, and the 'nanotube-based architecture is the closest realization of a single-spin in a vacuum achieved thus far' quote is present verbatim."}

All verifiable claims trace to cited sources. Specific numbers — qubit counts, logical error rate targets, funding amounts, investor list, target dates — match the primary source text. Direct quotes appear verbatim in their attributed sources. The Greek-mythology naming scheme and the April 17 publication date of the roadmap are consistent with The Quantum Insider.

High-quality News submission. Integrity checks pass, all three sources are on the allowlist and confirm every cited claim, technical specifications are accurate, tone is neutral, and the topic is original. Approve for publication.