French Startup C12 Unveils Four-Generation Roadmap to 100,000-Qubit Fault-Tolerant Quantum Computer by 2033 Using Carbon Nanotube Spin Qubits
Paris-based C12 published a four-stage plan to scale its carbon nanotube spin-qubit processors from 16 physical qubits in 2027 to over 100,000 by 2033, betting a solid-state modality can catch incumbents on error-corrected quantum computing.
Overview
Paris-based quantum computing startup C12 published a multi-generation hardware roadmap on April 17 that targets a utility-scale fault-tolerant quantum computer by 2033, according to The Quantum Insider. The plan lays out four successive systems built on carbon nanotube spin qubits, scaling from 16 physical qubits in 2027 to more than 100,000 by 2033.
The announcement places C12 alongside IBM, Google Quantum AI, and other established players that have published long-range roadmaps, but using a qubit modality that none of the incumbents pursue. The company’s bet is that ultra-pure carbon-12 nanotubes, paired with chiplet-based 3D integration, can deliver the combination of speed, fidelity, and manufacturability needed for error-corrected computing.
What We Know
The roadmap names each generation after a figure from Greek mythology and sets specific physical qubit counts, logical qubit counts, and logical error rate targets for each, per The Quantum Insider:
- Aïdôs (2027) — 16 physical qubits forming a single logical qubit, demonstrating C12’s first logical quantum operations at sub-microsecond physical gate speeds.
- Zélos (2030) — 236 physical qubits and 8 logical qubits at logical error rates of approximately 10⁻⁵. This generation introduces the full stack needed for modular scaling: chiplet packaging, cryogenic electronics, all-digital control signals, an on-chip qubit bias array, and multiplexed readout.
- Styx (2032) — 8,500 physical qubits and at least 128 logical qubits at logical error rates of 10⁻⁶, produced by replicating the Zélos chiplet unit many times.
- Panopeia (2033) — more than 100,000 physical qubits and roughly 800 logical qubits at logical error rates around 10⁻⁷, operating within a single cryostat at a sub-watt power budget per qubit and a 17-square-meter footprint.
CEO and co-founder Pierre Desjardins framed the strategy around architecture rather than raw qubit count, stating that the “real challenge is building quantum computers that can scale reliably,” according to The Quantum Insider. Chairman and CTO Matthieu Desjardins said the carbon nanotube platform allows the company to “design systems where quantum error correction and large-scale integration are efficient at scale,” per the same source.
C12’s qubits are electron spins trapped inside isotopically purified carbon-12 nanotubes suspended above silicon chips, according to The Quantum Insider. The same source reports that C12 has measured coherence times “two orders of magnitude larger than previously measured in carbon-based quantum circuits,” a figure the company cites as evidence that the carbon-12 platform suppresses nuclear-spin noise well enough to support fault-tolerant operation. The new roadmap’s processors combine this material with a superconducting quantum bus that provides all-to-all connectivity within a qubit zone, and with chiplet-based modular packaging that scaling from Zélos onward depends on, per The Quantum Insider.
The roadmap also formalizes C12’s turn toward quantum low-density parity-check (QLDPC) error-correcting codes. In March, C12 adopted QC Design’s Plaquette software platform to benchmark QLDPC codes against its high-connectivity architecture and to simulate how hardware imperfections affect logical qubit performance, as reported by The Quantum Insider.
C12 is not a new entrant to the sector. The company raised €18 million (about $19.4 million) in a pre-Series A round in June 2024, led by Varsity Capital, the European Innovation Council Fund, and Verve Ventures, with participation from 360 Capital, Bpifrance, and BNP Paribas Développement, according to SiliconANGLE. That article also describes the company’s nano-assembly process for integrating nanotubes onto silicon chips and C12’s claim that its “nanotube-based architecture is the closest realization of a single-spin in a vacuum achieved thus far.”
What We Don’t Know
The roadmap announcement specifies targets but does not disclose current performance. C12 has not publicly released two-qubit gate fidelities or physical error rates for its production devices in this release, only the sub-microsecond gate-speed target for Aïdôs, per The Quantum Insider. Without those figures, it is difficult to judge how much of the scaling challenge the company has already solved versus how much remains.
The company has also not disclosed fresh funding attached to the roadmap in the announcement reported by The Quantum Insider. Executing on a plan that requires fabricating, integrating, and packaging chiplets with 8,500 qubits by 2032 and over 100,000 by 2033 will require capital well beyond the €18 million pre-Series A raised in 2024, as documented by SiliconANGLE.
Analysis
The field’s roadmaps are converging on similar endpoints in the early 2030s — hundreds to a thousand logical qubits at error rates near 10⁻⁶ to 10⁻⁸ — but are diverging sharply on the physical modality used to get there. Superconducting transmons, trapped ions, neutral atoms, photons, and silicon spin qubits each come with distinct scaling tradeoffs. Carbon nanotube spin qubits have until now been a research curiosity rather than a commercial contender; C12’s roadmap is the first public attempt to position them as a credible path to fault tolerance.
The argument rests on three physical claims: that carbon-12 purification removes nuclear-spin noise well enough to sustain long coherence times, as suggested by C12’s reported two-orders-of-magnitude improvement over prior carbon-based circuits per The Quantum Insider; that electron-spin gate operations in the device can run at sub-microsecond speeds, per the Aïdôs target reported by The Quantum Insider; and that chiplet-based 3D integration can carry the architecture from hundreds of qubits at Zélos to six figures at Panopeia. If Aïdôs demonstrates a functioning logical qubit in 2027, C12 will have crossed the same threshold that has consumed billions of dollars of investment across the rest of the field. If it does not, the company will join the list of physical platforms that looked promising on paper but did not survive the transition from research lab to engineering reality.
The roadmap also sharpens the European quantum picture. A growing slice of the continent’s public and private quantum capital is flowing to hardware companies betting on qubit modalities where European teams lead the global research — neutral atoms at PASQAL, cat qubits at Alice & Bob, photonics at Quandela, and now carbon nanotubes at C12. Whether that research lead translates into competitive commercial hardware by the early 2030s is the bet that the French ecosystem, and the investors behind C12 documented by SiliconANGLE, is now making.