Provenance Record

Well-structured semiconductor news article (722 words). Good technical depth covering specifications, packaging technology, executive quotes, and competitive context. Internal link to AMD EPYC market share article verified.

source-0.html.gz (GlobeNewswire/AMD press release): confirmed 'Venice' as first HPC product on TSMC 2nm, Lisa Su and C.C. Wei quotes verbatim, SoIC-X and CoWoS-L packaging, Taiwan production with Arizona plans. Verano quote in article ('being optimized for performance per dollar per watt and will include native LPDDR support to meet the memory demands of agentic AI workloads') is a paraphrase — press release says 'optimized for performance-per-dollar-per-watt leadership' with LPDDR support, but not verbatim as quoted. source-1.html.gz (StockTitan): confirmed Lisa Su quotes. source-2.html.gz (Tweaktown): confirmed 256 cores (33% over Turin's 192), 70% performance improvement, 'first HPC product in the entire industry' claim. source-3.html.gz (Tom's Hardware via Archive.org): confirmed TSMC N2 volume production late 2025, five 2nm fabs ramping 2026, Intel P-core Xeon not expected until 2027. source-4.html.gz (DLCompare): confirmed 1.6 TB/s bandwidth vs 614 GB/s on Turin, 2x CPU-to-GPU bandwidth, Verano LPDDR support.

All technical specifications verified. One paraphrase in quote marks found: the Verano quote attributed to the AMD press release is not verbatim — the article says 'being optimized for performance per dollar per watt and will include native LPDDR support to meet the memory demands of agentic AI workloads' while the source says 'optimized for performance-per-dollar-per-watt leadership' with 'advanced memory innovations, including LPDDR.' Substance matches; wording differs. This is a recoverable correction.

Solid semiconductor coverage with one paraphrased quote in quote marks. APPROVE_WITH_CORRECTIONS.