AMD Begins Production Ramp of EPYC Venice on TSMC 2nm, First HPC Chip on Advanced Node

Overview

AMD announced on May 21, 2026 that its sixth-generation EPYC server processor, codenamed “Venice,” has entered production ramp on TSMC’s 2nm process technology in Taiwan — making it the first high-performance computing chip in the industry to reach volume manufacturing on the advanced node, according to the company’s official press release on GlobeNewswire. The milestone extends AMD’s server CPU momentum, which has seen EPYC capture a record 46.2 percent of server CPU revenue in Q1 2026.

What We Know

Venice on TSMC 2nm — a first for HPC. As noted by Tweaktown, “Venice is the first high-performance computing (HPC) product in the entire industry to enter volume production on TSMC’s advanced 2nm process node.” Tom’s Hardware reported that TSMC began N2 volume production in late 2025 and is ramping five separate 2nm fabs in 2026 due to record demand, but that server processors face greater yield qualification challenges than smartphone chips due to larger die sizes and architectural complexity — making Venice’s production ramp a more demanding feat than Apple’s earlier consumer silicon adoption of the node.

Specifications. According to Tweaktown, Venice is built on AMD’s Zen 6 architecture and scales up to 256 cores, a 33 percent increase over the current EPYC Turin lineup’s maximum of 192 cores. DLCompare reported that per-socket memory bandwidth is expected to rise to 1.6 TB/s, more than doubling the 614 GB/s available on Turin processors, and that CPU-to-GPU bandwidth is also getting a 2x increase.

Performance claims. AMD projects a 70 percent performance improvement over Turin, as reported by Tweaktown and Tom’s Hardware.

Advanced packaging. The AMD press release stated that Venice uses TSMC’s SoIC-X and CoWoS-L advanced packaging technologies to achieve its memory and bandwidth targets.

Verano follow-on. Alongside the Venice announcement, AMD disclosed a follow-on 6th Gen EPYC processor codenamed “Verano.” According to DLCompare, Verano will prioritize efficiency and AI workloads with LPDDR memory support. The AMD press release stated that Verano is “being optimized for performance per dollar per watt and will include native LPDDR support to meet the memory demands of agentic AI workloads.”

Manufacturing location and US plans. According to Tweaktown, production is currently underway at TSMC’s facilities in Taiwan, with plans to later extend the ramp to TSMC’s Arizona fabrication plant.

Executive statements. Dr. Lisa Su, AMD’s Chair and CEO, said in the press release: “Ramping ‘Venice’ on TSMC 2nm process technology marks an important step forward in accelerating the next generation of AI infrastructure.” She also stated: “Our deep partnership with TSMC is helping AMD bring leadership compute technologies to market with the speed and scale required.”

Dr. C.C. Wei, Chairman and CEO of TSMC, said: “Our close collaboration with AMD reflects the importance of pairing leadership process technology with advanced design innovation.”

What We Don’t Know

AMD has not disclosed a specific launch date for EPYC Venice — only that production ramp has begun, with customer availability expected in the second half of 2026. Volume shipment timelines and initial pricing have not been announced. It also remains unclear how quickly yields on the 2nm node will scale to meet hyperscaler demand, given that server-class HPC chips face more demanding qualification requirements than consumer products, as Tom’s Hardware noted.

AMD has not confirmed whether the 70 percent performance improvement figure is based on raw compute throughput, per-watt efficiency, or workload-specific benchmarks, and has not published independent third-party validation of the claim.

Analysis

The production ramp of Venice marks a convergence of two simultaneous leadership claims: the first HPC chip on TSMC’s most advanced node, and the continuation of a server CPU competitive trajectory that has brought AMD from single-digit market share five years ago to the verge of parity today. Tom’s Hardware noted that Intel’s competing P-core Xeon processors are not expected until 2027 at the earliest, giving AMD a potential window of several quarters on the leading process node.

The 1.6 TB/s memory bandwidth figure — more than 2.6 times the current generation — reflects a design philosophy tuned for AI inference and training workloads, where data movement between CPU and memory typically bottlenecks throughput. The addition of Verano with native LPDDR support suggests AMD is also targeting the growing segment of agentic AI deployments that require dense compute at lower power envelopes, complementing the high-core-count Venice optimized for scale-out cloud infrastructure.