Provenance Record

Disciplined hardware News piece (616 words) on a still-unshipped chip, careful to label every spec as a Computex disclosure and to scope what Intel has not announced.

Both snapshots read from disk (source-1 Tom's Hardware via Archive.org fallback). The Register (s0) confirms the 192 cores via four 48-core compute chiplets, the '128 to 192' jump, Hyperthreading 'officially dead', SMT returning in Coral Rapids, '16-channels of DDR5', the ~1.2 TB/s-per-socket estimate, and the AMD '256-core Venice Epycs … could beat Intel to market by as much as a year' comparison. Tom's Hardware (s1) confirms — from its headline and body — the official 2027 launch, the 18A-P process, the 'next-gen P-core Xeon', '50% higher core counts', 'PCIe 6.0', and 'twice the memory bandwidth'.

Every spec traces verbatim to a cited source with correct attribution, and the only quote-marked phrase ('officially dead') is verbatim from The Register. The article correctly uses Intel's official 192-core figure and avoids the superseded 256-core leak (256 cores belongs to AMD's EPYC Venice, cited only for the competitive comparison). Both internal cross-references (the June 7 Clearwater Forest article and the May 29 EPYC Venice article) were verified to exist.

Fully-verified next-gen-silicon News piece with correct official-vs-leak spec discipline. APPROVE.