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Europe's First Academic RISC-V Chip on Intel 3 Node Passes Validation as Open Silicon Hits 25 Percent Market Share

Barcelona Zettascale Lab's Cinco Ranch TC1, a three-core RISC-V chip fabricated on Intel's 3nm process, has passed validation testing, marking a milestone in Europe's push for semiconductor sovereignty.

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Overview

The Barcelona Zettascale Lab (BZL), a joint effort led by the Barcelona Supercomputing Center (BSC-CNS) and Intel, has announced that its Cinco Ranch TC1 chip has successfully passed experimental bring-up and validation testing. The TC1 is the first chip designed in an academic setting to be fabricated on Intel’s advanced 3-nanometer (Intel 3) process node, and it runs entirely on open-source RISC-V processor cores developed in Spain. The milestone arrives as the RISC-V instruction set architecture has crossed the 25 percent threshold of the global processor market, according to RISC-V International, reinforcing Europe’s bet that open silicon can deliver genuine semiconductor sovereignty.

The Cinco Ranch TC1

The TC1 integrates a heterogeneous architecture composed of three independent processing tiles, each built around a different RISC-V core designed at BSC, as detailed in the lab’s official announcement. The three cores target distinct workload profiles:

  • Sargantana — an in-order, single-issue RV64G core with custom extensions for genomics sequence alignment, representing the third generation of BSC’s Lagarto processor family and the first to break the gigahertz barrier.
  • Lagarto Ka — a dual-issue, out-of-order core featuring a 16-lane Vitruvius vector processing unit compliant with the RVV 1.0 specification, aimed at math-intensive and AI workloads.
  • Lagarto Ox — a six-way out-of-order RV64GC core designed for general-purpose scalar performance.

The chip also includes a three-level cache hierarchy with a shared L3 cache based on the open-source OpenPiton framework, and supports DDR5 memory and PCIe Gen3 interfaces. According to Wccftech, the heterogeneous approach differs from conventional performance/efficiency core configurations found in mainstream commercial processors, instead targeting extreme workload granularity for specialized optimization.

Validation Results

Linux was first successfully booted on the TC1 in May 2025, and characterization work began in July 2025 after the lab received a batch of 500 fabricated chips, according to the BSC press release. The chip reached an operating frequency of 1.25 GHz, exceeding initial design estimates.

Miquel Moreto, BSC researcher and hardware coordinator of BZL, stated that “successfully booting Linux in a stable manner and verifying that the chip reaches the expected frequencies confirms the maturity of the design and the quality of the work carried out by the BZL teams.” The lab also reported a high percentage of fully functional chips from the fabrication batch, and noted that the design was validated against TSMC’s N7 node in addition to Intel 3 to ensure robustness.

European Sovereignty in Silicon

The TC1 is part of a broader European effort to reduce dependence on non-European processor architectures. The chip traces its lineage to the DRAC (Designing RISC-V-based Accelerators for next generation Computers) project, a multi-institution Spanish initiative that produced the Lagarto processor family beginning in 2019. BSC coordinates the effort alongside partners including the Universitat Politecnica de Catalunya, Universitat Autonoma de Barcelona, and the Institut de Microelectronica de Barcelona.

At the continental level, the work feeds into the European Processor Initiative (EPI) and the newer DARE (Digital Autonomy with RISC-V in Europe) project, which has received up to 120 million euros in EU funding through the Horizon Europe program with additional co-funding from 13 participating countries. According to EuroHPC JU, the DARE consortium of 38 partners is developing three core components: a vector accelerator for high-precision computing, an AI Processing Unit for inference acceleration, and a general-purpose processor optimized for European supercomputing workloads. The framework partnership agreement runs through 2030.

RISC-V’s Growing Footprint

The TC1 validation comes against a backdrop of rapid RISC-V adoption worldwide. As reported by Tom’s Hardware, RISC-V International has announced 25 percent market penetration, ahead of earlier industry projections that did not foresee that level until 2030. The ratification of the RVA23 profile standard in late 2024 added mandatory vector and hypervisor extensions, establishing a baseline for software portability across application processors and enabling Android support on RISC-V hardware.

Industry investment is accelerating accordingly. Qualcomm acquired RISC-V server chip designer Ventana Microsystems in December 2025, gaining access to the Veyron V2 chiplet design with up to 32 RVA23-compatible cores clocked at 3.85 GHz. Canonical has announced plans to deepen RISC-V support in Ubuntu 26.04 LTS. And the upcoming Embedded World 2026 conference in Nuremberg will feature a dedicated RISC-V pavilion addressing automotive, IoT, and industrial applications.

What We Don’t Know

Several questions remain. The TC1 is a research vehicle, not a commercial product, and the path from validated test chip to production-ready European processors remains long and expensive. The chip’s 1.25 GHz clock speed, while exceeding expectations for an academic design, is far below what commercial RISC-V offerings from companies like Ventana or SiFive can achieve. How quickly the DARE project’s 2030 roadmap can translate laboratory results into competitive silicon for European supercomputers is an open question.

The Intel 3 process node used for fabrication is also not Intel’s most advanced technology, and future iterations of European RISC-V designs will need to track Intel Foundry’s roadmap — or find alternative manufacturing partners — to remain competitive. Whether Europe’s fragmented funding model, spread across dozens of institutions and countries, can match the pace set by concentrated commercial R&D efforts in the United States and Asia remains to be seen.

Looking Ahead

The BZL team is now proceeding with full functional and performance testing, software optimization, and system validation on the TC1. The lab’s next step is to scale the architecture toward designs suitable for high-performance computing, guided by the DARE project’s goals. With Embedded World 2026 approaching in March and the RISC-V Summit Europe scheduled later in the year, European RISC-V development is entering a phase where laboratory validation must give way to demonstrating real-world competitiveness.