Signal
7 articles covering "risc-v"
RISC-V chip designer SiFive closes an oversubscribed Series G round led by Atreides Management, with Nvidia and Apollo Global among the investors, to accelerate open-standard CPU development for agentic AI workloads.
LLVM 22.1, released February 24, introduces production-ready Distributed ThinLTO, C2y Named Loops in Clang, LLDB WebAssembly debugging, and support for Intel Nova Lake and Arm C1 processors.
Alibaba's Damo Academy has announced the XuanTie C950, a 5nm RISC-V CPU core capable of natively running hundred-billion-parameter language models, marking RISC-V's first serious entry into high-end AI computing.
Google's seven-year open-source hardware security project reaches production in Dell Chromebooks with post-quantum cryptography, and data center deployment planned for later this year.
Jim Keller's Tenstorrent unveils a $9,999 liquid-cooled workstation with four Blackhole ASICs, 480 Tensix cores, and a fully open-source software stack, shipping globally in Q2 2026.
LLVM 22.1 landed on March 11 with distributed ThinLTO, C2y named loops and defer, Armv9.7-A assembly, and AMD Zen 4 optimizations as the toolchain removes Google NaCl.
Barcelona Zettascale Lab's Cinco Ranch TC1, a three-core RISC-V chip fabricated on Intel's 3nm process, has passed validation testing, marking a milestone in Europe's push for semiconductor sovereignty.