XCENA Raises $135 Million Series B for CXL Computational Memory Packing Thousands of RISC-V Cores Beside DRAM
South Korean startup XCENA raised a $135M Series B at a $570M valuation for its MX1 CXL memory device, betting AI's real bottleneck is memory, not compute.
Overview
XCENA, a South Korean chip startup, has raised a $135 million Series B round at a $570 million valuation to commercialize a new class of memory hardware that places thousands of processing cores directly next to DRAM, according to TechCrunch. The company’s wager is that the constraint slowing modern AI systems is not raw compute but the cost of shuttling data back and forth between processors and memory.
What We Know
The round was co-led by Atinum and IMM Investment, with participation from Corstone Asia and existing backers SBI Investment and Mirae Asset Capital, bringing XCENA’s total funding to $185 million, as reported by TechCrunch. Founded in 2022 and employing more than 90 people across offices in Pangyo, South Korea, and Sunnyvale, California, the company is led by Jin Kim, with Dohun Kim as chief technology officer and Harry Juhyun Kim as chief product officer, TechCrunch reported.
The company’s flagship product, the MX1, is a memory device that connects to a host processor over CXL, the Compute Express Link interconnect that TechCrunch describes as “essentially a dedicated express lane between the processor and memory.” Rather than moving data to the CPU to be processed, the MX1 carries out computation on the data “before it ever needs to leave the memory module,” according to the same report. The architecture is RISC-V based and integrates thousands of cores, TechCrunch noted.
Detailed specifications disclosed by ServeTheHome describe the MX1 as a CXL 3-class device built on a PCIe Gen6 interface, with on-card support for up to 1TB of DDR5-8400 memory across a quad-channel layout using 256GB DIMMs, plus the ability to back capacity with SSDs. ServeTheHome reported two variants: the MX1P, with a single PCIe Gen6 x8 link, and the MX1S, slated for 2026, which adds dual PCIe Gen6 x8 links and CXL 3.2 support.
The near-data-processing pitch is one XCENA’s founder has made repeatedly. “AI infrastructure was hitting a memory wall, not a compute limit. CPU and GPU performance kept improving, but memory capacity, bandwidth, and data movement were becoming primary bottlenecks,” co-founder and CEO Jin Kim told Blocks & Files. “The core inefficiency in AI systems was and still is data movement,” he added, explaining that the MX1 “allows operations like vector search and analytics to run directly on the data.” Speaking to TechCrunch, Kim framed the gap more bluntly: “CPUs and GPUs have both gotten smarter over the decades. Memory never did.”
XCENA plans to manufacture the MX1 at a Samsung foundry, with production scheduled for the end of 2026 and revenue expected to begin in 2027, according to TechCrunch.
What We Don’t Know
XCENA has not publicly disclosed the exact number of RISC-V cores on the MX1 or independent benchmarks demonstrating its claimed efficiency gains. The company says the device could let workloads “that used to require 10 servers” potentially run on a single server, per TechCrunch, but that figure is a company projection rather than a measured result, and the report does not specify the workloads it applies to. It also remains unclear how broadly CXL 3-class hardware will be adopted by server makers, since the standard depends on host platforms and operating-system support that are still maturing.
Analysis
XCENA enters a crowded field of companies arguing that memory, not silicon logic, is the binding constraint on AI infrastructure. Its bet on computational memory tied to CXL is distinctive in coupling near-data processing with the pooled, expandable memory that the interconnect enables. Whether the approach displaces conventional architectures will hinge on real-world performance once the MX1 reaches production and on how quickly the broader CXL ecosystem matures around it.