Tensordyne Sends Its Logarithmic-Math AI Chip Napier to TSMC, Claiming Four Times the Speed at a Fifth the Power of an Nvidia GB300 System
The startup says its 3nm Napier inference chip turns matrix multipliers into adders, with commercial sales of a 72-chip system slated for the second half of 2027.
Overview
AI-inference startup Tensordyne has sent the design of its first chip, Napier, to be manufactured, and claims the part can run large language models four times as fast while drawing one-fifth the power of an equivalent Nvidia system. According to IEEE Spectrum, “the company just sent the plans for its first chip to be manufactured, with commercial sales of a 72-chip system scheduled for the second half of 2027.” The chip’s central bet is an unusual one: doing AI math in logarithms so that the silicon can replace multipliers with much cheaper adders.
What We Know
Napier is built around a logarithmic number system. The approach exploits a basic identity of logarithms, which IEEE Spectrum describes as the fact that “the logarithm of A times B equals the logarithm of A plus the logarithm of B.” Because addition is far cheaper to implement in transistors than multiplication, the technique reduces the silicon and energy cost of the matrix math that dominates LLM inference. “We’ve turned multipliers into adders,” Gilles Backhus, a Tensordyne founder and vice president of AI, told IEEE Spectrum.
The headline performance claim is comparative. Tensordyne says its 72-chip system can run large LLMs “four times as fast using one-fifth the power compared to a 72-Nvidia GB300 system,” according to IEEE Spectrum. In its own announcement, Tensordyne frames the gain differently, saying Napier delivers “up to 17x more tokens per watt and 13x higher throughput than NVIDIA Blackwell systems,” per the company’s press release.
On the hardware itself, each Napier chip “includes 144 gigabytes of HBM,” IEEE Spectrum reports. The company describes a rack-scale product it calls the TDN72 Inference Pod, with the silicon going “into production at TSMC on its 3nm process node,” according to Tensordyne. The system is built “in partnership with Broadcom and HPE Juniper Networks,” the company said.
Tensordyne offers a concrete operating example for its rack. “A four-pod rack working on a 2-trillion parameter LLM would deliver 1,300 tokens per-second per-user at a cost of US $11 for 1 million tokens, while consuming 120 kilowatts of power,” according to IEEE Spectrum.
The company, which says it is “headquartered in Sunnyvale, California and Munich, Germany,” pitched the design as a way out of a familiar bind. “The market is hungry for fast AI; customers want speed, but achieving it has always meant accepting prohibitive costs,” said chief executive Marc Bolitho in the announcement. R.K. Anand, chief product officer and co-founder of Tensordyne, told IEEE Spectrum: “We’re optimizing for two hard challenges here at the same time. We’re the first company proving that you can do both without going to multiple vendors and multiple racks.”
Tensordyne says the program already has commercial interest, citing “more than $200 million in forecasted Napier system demand,” in its release. Frank Ostojic, Senior Vice President and General Manager, ASIC Products Division at Broadcom, said in the same announcement: “We are happy to support the Tensordyne team as our partner & customer.”
What We Don’t Know
Napier’s claims rest on simulations and design projections rather than shipped silicon. The chip has only just gone to manufacturing, and IEEE Spectrum notes that commercial sales of the 72-chip system are “scheduled for the second half of 2027” — leaving more than a year before independent benchmarks against Nvidia’s hardware are possible. Tensordyne “plans to have a beta version available through the cloud for customers to work with,” according to IEEE Spectrum, but the company’s two stated comparisons use different Nvidia baselines — a GB300-based system in one case and “Blackwell systems” in the other — and neither has been validated by an outside party.
Accuracy is the other open question for any logarithmic-math accelerator. Converting between linear and logarithmic representations introduces approximation, and whether Napier preserves output quality across diverse models at its claimed throughput will only be settled once customers run their own workloads on real hardware.