AMD's CDNA 5 Architecture Detailed: Inside the Instinct MI455X's 320-Billion-Transistor Design
A ServeTheHome deep dive breaks down CDNA 5, the architecture behind AMD's Instinct MI455X, alongside the ROCm.ai tooling meant to let AI coding agents program AMD GPUs natively.
Editor's Note ·
- Correction:
- The article quotes Network World as calculating that Nvidia's Rubin platform has "50% less capacity than AMD's offering." Network World's article actually reads: "Rubin is expected to deliver approximately 50 PFLOPS of FP4 performance but has 288GB of HBM4 memory, 50% less than Instinct." The underlying fact — Rubin's 288GB of HBM4 is roughly half the MI455X's 432GB — is accurate and supported by the source, but the quoted wording does not match the outlet's original phrasing.
Overview
A technical deep dive published August 12 by ServeTheHome lays out the architecture behind AMD’s Instinct MI455X, the flagship accelerator AMD introduced at its Advancing AI 2026 event in San Francisco on July 23. The chip is built on a new architecture AMD calls CDNA 5, and ServeTheHome’s analysis puts hard numbers on a design the outlet describes as “a chip with 320 billion transistors, a 72% increase from the previous generation.”
What We Know
- The MI455X compute die is built on TSMC’s N2 process node, and AMD equipped the chip with “12 stacks of HBM4 memory, 4 more stacks than the MI355X,” its prior-generation accelerator, according to ServeTheHome.
- At 36GB per stack, that works out to 432GB of local memory per chip, according to ServeTheHome, a figure independently confirmed by Network World, which reports the MI455X “boasts 320 billion transistors, 432GB of HBM4 memory, and up to 40 petaflops of FP4 AI compute.”
- Memory bandwidth reaches 23.3 TB/second, which ServeTheHome says is “2.9x the bandwidth of the MI355X.” Network World separately reports the same 23.3 TB/s figure, noting it slightly exceeds Nvidia’s competing Rubin platform, which it puts at 22 TB/s.
- On raw compute, ServeTheHome measured “a bit over 40 PFLOPS of dense FP4 tensor operations or half that for FP6 and FP8,” plus 315 TFLOPS of FP32/FP16 vector throughput. Network World frames the FP4 figure as roughly doubling AMD’s prior Instinct MI350 generation.
- Chip-to-chip networking runs over AMD’s Ultra Accelerator Link, which ServeTheHome measured at “3.6TB/second of bandwidth.” Power draw was not officially disclosed; ServeTheHome estimates the chip runs “somewhere north of 2 kW per GPU,” consistent with AMD fitting only four of them into each Helios compute tray.
- At rack scale, AMD’s own announcement says its Helios system combines 72 MI455X GPUs with 18 sixth-generation EPYC CPUs, a configuration Network World separately reports delivers “up to 31TB of HBM4 memory and as much as 2.9 exaflops of FP4 AI compute” per rack. AMD says the combined system delivers “up to 30% more tokens per dollar than the leading competitive solution.”
- Nvidia’s competing Rubin platform is expected to deliver approximately 50 PFLOPS of FP4 performance but with 288GB of HBM4 memory, which Network World calculates as “50% less capacity than AMD’s offering.”
- Alongside the MI455X, AMD’s Advancing AI announcement introduced the Instinct MI430X, which the company says is “the most advanced for HPC and sovereign AI with up to 288 TFLOPS of hardware-based FP64 performance for scientific computing.”
- On the software side, AMD is pairing the new silicon with a developer platform called ROCm.ai. According to AMD, “ROCm.ai brings AI-assisted GPU programming to developers by enabling popular coding agents such as Claude, Codex and Cursor to understand AMD platforms and ROCm natively.” AMD also says it is working with OpenAI, and that “leveraging OpenAI’s Triton framework with AMD ROCm software, the companies are optimizing GPT-class workloads on AMD Instinct MI455X GPUs.”
- “The next phase of AI will span frontier models, agents and physical AI, creating new opportunities to bring intelligence everywhere,” said Dr. Lisa Su, chair and CEO of AMD, in the company’s announcement. “Realizing that potential will take the entire industry working together. AMD is partnering across the ecosystem to deliver leadership compute and open platforms that give customers the performance, flexibility and choice to scale AI from the data center to the edge.”
What We Don’t Know
AMD has not officially disclosed per-GPU power consumption for the MI455X; ServeTheHome’s “north of 2 kW” figure is an estimate derived from the Helios tray configuration, not a confirmed AMD spec. Independent, third-party benchmark results comparing the MI455X against Nvidia’s Rubin platform have not yet been published — the throughput and cost comparisons cited above come from AMD’s own claims and from Network World’s analysis of AMD’s disclosed specifications against Nvidia’s publicly expected Rubin figures.
Analysis
ServeTheHome frames CDNA 5 as one of AMD’s most substantial server-GPU architecture changes in years, built around the jump to TSMC’s N2 process and a near-tripling of memory bandwidth generation-over-generation. Network World casts the launch explicitly in competitive terms, writing that the MI455X “narrows the hardware gap considerably, offering competitive AI compute alongside substantially more memory than Nvidia’s Rubin architecture.” The ROCm.ai push toward coding-agent compatibility with Claude, Codex, and Cursor also signals that AMD is trying to lower the software switching cost that has historically kept AI developers tied to Nvidia’s CUDA ecosystem, pairing the new hardware with tooling aimed directly at how AI-assisted software engineering is increasingly done.