AMD Unveils MI400 Series on TSMC 2nm and Helios Rack-Scale AI Platform as Delay Rumors Swirl
AMD's Instinct MI400 family debuts three CDNA 5 accelerators on TSMC 2nm alongside the 72-GPU Helios rack, but a production timeline dispute clouds the second-half 2026 launch.
AMD used its CES 2026 keynote in January to reveal the full Instinct MI400 product family and the Helios rack-scale AI platform, marking the company’s most ambitious push yet into the data center AI accelerator market dominated by Nvidia. The announcement introduced three GPU variants built on the new CDNA 5 architecture and TSMC’s 2nm process node, alongside a double-wide rack system designed to compete directly with Nvidia’s NVL72 offering. A subsequent dispute over production timelines in February has added uncertainty to what AMD calls an on-track second-half 2026 launch.
Three Chips for Three Workloads
The MI400 series comprises three accelerators targeting different segments of the AI infrastructure market: the MI430X, MI440X, and MI455X.
The flagship MI455X packs 320 billion transistors across 12 chiplets, fabricated on a combination of TSMC 2nm and 3nm process nodes. Each MI455X carries 12 stacks of 36 GB HBM4 memory, totaling 432 GB per accelerator. The chip is designed primarily for large-scale AI training and inference in rack-scale deployments.
The MI440X targets eight-way system nodes as a direct replacement for the MI300 and MI350 product lines, serving customers who need a drop-in upgrade path without migrating to full rack-scale infrastructure. The MI430X rounds out the family with full FP32 and FP64 precision support, addressing traditional high-performance computing workloads alongside AI tasks — a dual-purpose capability that neither the MI440X nor MI455X prioritize.
Helios: 72 GPUs in a Single Rack
The Helios platform represents AMD’s first rack-scale system, developed in collaboration with Meta Platforms using the Open Rack Wide v3 specification. The double-wide chassis weighs nearly 7,000 pounds and houses 18 compute trays, each containing four MI455X accelerators and one EPYC Venice CPU based on the Zen 6 architecture.
In total, a single Helios rack delivers 72 MI455X GPUs, 18,000 compute units, and 4,608 CPU cores. AMD claims the system produces 2.9 exaflops of FP4 compute performance and 1.4 exaflops of FP8 performance for AI training, with 31 TB of aggregate HBM4 memory and 1.4 PB/s of memory bandwidth. A planned double-wide Helios variant would scale to 128 MI455X accelerators, targeting up to 3 AI exaflops in a single rack.
AMD’s $4.9 billion acquisition of ZT Systems in August 2024 underpins the Helios manufacturing strategy. The company subsequently sold ZT’s manufacturing arm to Sanmina for $3 billion, retaining the design expertise while outsourcing physical production.
The Delay Dispute
In mid-February 2026, semiconductor research firm SemiAnalysis published a report claiming that engineering samples and low-volume production of the MI455X-based Helios system would arrive in the second half of 2026, but that mass production would slip to the second quarter of 2027. The report cited potential thermal design issues as a contributing factor.
AMD pushed back forcefully. Forrest Norrod, AMD’s executive vice president for the Data Center Solutions Group, stated that the company had “no significant thermal issue” and that the thermal design risk “was retired quite some time ago.” AMD’s corporate vice president of software development, Anush Elanganov, was more direct, calling the delay assessment “wrong” and writing that the MI455X was “right on target for shipments in 2H2026.”
The dispute hinges partly on definitions. SemiAnalysis distinguished between initial shipments and mass production ramp, while AMD’s statements emphasized that the product remains on schedule without specifying volume targets. Analysts noted that AMD did not disclose any delays in its most recent quarterly earnings, and that a material schedule slip would carry regulatory disclosure obligations under SEC rules.
Competitive Context
The MI400 launch arrives as competition in the AI accelerator market intensifies. Nvidia’s Vera Rubin platform, based on the Blackwell Ultra architecture, is expected in the second half of 2026, with some reports suggesting the VR200 rack systems could arrive ahead of schedule. Google’s seventh-generation Ironwood TPU, optimized for inference, entered general availability in late 2025, and Amazon’s Trainium3 on TSMC’s 3nm process began deployment in early 2026.
AMD has also outlined its next-generation MI500 series, projected for 2027, with claims of a 1,000-fold AI performance increase over the MI300X generation. Whether the MI400 family ships on time and in volume will determine whether that roadmap carries credibility with hyperscale buyers who are actively diversifying their chip procurement strategies across multiple vendors.
The initial Helios systems will use UALink over Ethernet rather than native UALink interconnect, which may limit inter-GPU bandwidth in early deployments compared to Nvidia’s NVLink-based systems. AMD has not disclosed when native UALink support will be available.